MSE908JB8资料

MSE908JB8_3K45H

Rev. 1, 8/2006

Mask Set Errata for Mask 3K45H

Introduction

This mask set errata applies to the mask 3K45H for these products:•

MC68HC908JB8

MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numericaldigits, and a letter, for example 3K45H. All standard devices are marked with a mask set number and adate code.

USB ResetDescription

SE116-USB

When the USB module is enabled, the USB reset disable bit (RSTD) in the configuration register(CONFIG) is cleared and a USB reset is detected, there is a small chance the device will fail.

©Freescale Semiconductor, Inc., 2006. All rights reserved.

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Workaround

WhentheUSBmoduleisenabledandaUSBresetisdetected,eitheraninternalresetoraninterrupttothe CPU can be generated. Which one is generated depends on the RSTD bit of CONFIG.

Configuring the USB reset to generate a USB interrupt request to the CPU by setting the RSTD bit ofCONFIGfixesthisproblem.WhenaUSBresetisdetectedintheinterruptroutines,youhavetwochoices:••

Reconfigure the USB module and other related registersUse software to cause a device reset, for example, illegal opcode

Example code to implement an illegal opcode:

USB_ISR:

brclr b_RSTF,UIR1,No_USB_Reset ;check USB resetdb$32;illegal opcodeNo_USB_Reset

Power-Up from LVRDescription

SE115-Power

Afewdevicesstartabnormallyduringpower-up.Theissueisthereleaseofthelowvoltagereset(LVR)earlier than the VREG reaching the CMOS logic operating voltage (typical 0.65 V).

The LVR takes the VDD but not the VREG as a reference. LVR exists until the VDD reaches the LVRthresholdvoltage(VLVR).TheproblemhappensinfewdeviceswhentheVDDrisesquicklyandtheVREGrisesslowly.IftheLVRhasbeenreleasedbuttheVREGdoesn’treachtheCMOSlogicoperatingvoltage,theLVRdoesnothaveanyeffect.ThismightcausetheinternallogictoimproperlyinitializeandtheMCUmight not start normally.

Therefore, the VDD voltage must be lower than the VLVR minimum (2.8 V) when the VREG voltagereaches the CMOS logic operating voltage.Workaround

Tofixtheproblem,adda10ΩseriesresistorbetweenthepowersupplyandtheVDD,andplacea10µFcapacitor at the VDD pin and a 4.7µF capacitor at the VREG pin.

Mask Set Errata for 908JB8, Mask 3K45H2Freescale Semiconductor元器件交易网www.cecb2b.com

MCUVDDVSSVREG0.1µF+10Ω10µF0.1µF+4.7µFVDDGlitch on Timer Buffered PWM Output

SE30-PWM

In timer buffered PWM operation, when a timer overflow (TOF) event or an output compare (OC) eventcoincideswithawritetoeitherpairofthetimerchannelregisters(TCHxH/L),thedutycycleatthePWMoutput glitches to 0% or 100% momentarily, then returns to proper operation.

ToavoidtheglitcheswhenchangingthePWMdutycycle,donotwritetoeitherpairofthetimerchannelregisters at the TOF or OC.

For example, in the TOF interrupt service routine: If the OC occurs near the last TOF, write to the timerchannel registers after the OC; if the OC occurs near the next TOF, write to the timer channel registersbeforetheOC.Awritetothechannelregisterhighbyte(TCHxH)shouldimmediatelyfollowedbyawriteto the low byte (TCHxL) to avoid TOF or OC occurring between the writes. Instruction cycle times mustbe included when making timing calculations.

The figure below shows a typical timer buffered PWM output waveform, indicating the TOF and OCevents.

Mask Set Errata for 908JB8, Mask 3K45HFreescale Semiconductor3元器件交易网www.cecb2b.com

TOFOCTOFOCTOFOCTOFTOFOCTimer bufferedPWM output

Pulse widthPeriodNOTES:

Do not write to either pair of timer channel registers at:TOF (timer overflow), or

OC (timer output compare) edges.

In buffered PWM, the pulse width is defined by the last written pair of timer channel registers.

Each pair of timer channel registers consist of a high byte register (TCHxH) and a low byte register (TCHxL).

Mask Set Errata for 908JB8, Mask 3K45H4Freescale Semiconductor