library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qudong_8 is
port(clk:in std_logic; --动态显示刷新速度时钟
QQ:in std_logic_vector(31 downto 0); 位
--32位BCD码输入，最0~3低位，28~31最高
qudong1:out std_logic_vector(7 downto 0); --驱动信号输出，0~7分别为abcdefgp
contrl:buffer std_logic_vector(2 downto 0)); --数码管位选输出，000最低位数码管有效，111最高位数码管有效
end qudong_8;
architecture behavior of qudong_8 is
signal disp:std_logic_vector(3 downto 0);
signal temp:std_logic_vector(2 downto 0);
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====Word行业资料分享--可编辑版本--双击可删====
begin
process(clk)
begin
if clk'event and clk='1' then
temp<=temp+1;
end if;
contrl<=temp;
end process;
process(contrl) --位选信号产生进程
begin
case contrl is
when\"000\"=>disp<=QQ(3 downto 0);
when\"001\"=>disp<=QQ(7 downto 4);
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when\"010\"=>disp<=QQ(11 downto 8);
when\"011\"=>disp<=QQ(15 downto 12);
when\"100\"=>disp<=QQ(19 downto 16);
when\"101\"=>disp<=QQ(23 downto 20);
when\"110\"=>disp<=QQ(27 downto 24);
when\"111\"=>disp<=QQ(31 downto 28);
when others=>disp<=\"0000\";
end case;
end process;
process(disp) --译码进程
begin
case disp is
when\"0000\"=>qudong1<=\"00111111\";
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====Word行业资料分享--可编辑版本--双击可删====
when\"0001\"=>qudong1<=\"00000110\";
when\"0010\"=>qudong1<=\"01011011\";
when\"0011\"=>qudong1<=\"01001111\";
when\"0100\"=>qudong1<=\"01100110\";
when\"0101\"=>qudong1<=\"01101101\";
when\"0110\"=>qudong1<=\"01111101\";
when\"0111\"=>qudong1<=\"00000111\";
when\"1000\"=>qudong1<=\"01111111\";
when\"1001\"=>qudong1<=\"01101111\";
when others=>qudong1<=\"00000000\";
end case;
end process;
end behavior;
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