Memory module and memory system

专利名称：Memory module and memory system发明人：Yoshinori Matsui,Toshio Sugano,Hiroaki

Ikeda

申请号：US11492981申请日：20060726

公开号：US20060262587A1公开日：20061123

专利附图：

摘要：In a memory module including a plurality of DRAM chips which transmit/receivea system data signal with a predetermined data width and at a transfer rate and whichtransmit/receive an internal data signal having a larger data width and a lower transfer

rate as compared with the system data signal, the transfer rate of the system data signalis restricted. Current consumption in DRAMs constituting the memory module is large,hindering speed increases. For this memory module, a plurality of DRAM chips arestacked on an IO chip. Each DRAM chip is connected to the IO chip by a through

electrode, and includes a constitution for mutually converting the system data signal andthe internal data signal in each DRAM chip by the IO chip. Therefore, wiring between theDRAM chips can be shortened, and DLL having a large current consumption may bedisposed only on the IO chip.

申请人：Yoshinori Matsui,Toshio Sugano,Hiroaki Ikeda

地址：Tokyo JP,Tokyo JP,Tokyo JP

国籍：JP,JP,JP

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